module pipeline (input reset, input clk); 			   
	
	wire wire_stop;/*AQUEST CABLE SURT DE ON VINGUI EL PUTU STOP!!! OK???*/
	
	wire[15:0] wire_FeFe_pcin, wire_FeFe_pcout;
	wire[81:0] wire_FeDeIn, wire_FeDeOut; 
	wire[16:0] wire_DeFeIn, wire_DeFeOut;
	wire wire_DeFe_enable, wire_DeFe_itlbwr, wire_DeFe_itlbwridx, wire_jumpsys,
	wire_DeFe_itlbwren, wire_AlDe_salt, wire_DeAl_ff_NOP;
	wire[207:0] wire_DeAlIn, wire_DeAlOut;
	wire[59:0] wire_DeWbIn, wire_DeWbOut;
	wire[2:0] wire_DeWb_regBypassA, wire_DeWb_regBypassB;
	wire wire_DeWb_TypeA, wire_DeWb_TypeB; 							
	/*************** Sortida Cables WriteBack**********/
	wire [15:0] WbDe_pc,WbDe_exceptionWrite, WbBus_addressWrite, WbBus_adressWrite;
	wire [31:0] WbDe_valueBypassA, WbDe_valueBypassB, WbBus_dataWrite;
	wire WbDe_validBypassA, WbDe_validBypassB, WbDe_STROB, WbDe_inout, WbBus_valid, WbFe_interruption;
	wire [3:0] WbDe_issue, WbBus_destinyWrite;  
	wire [2:0] WbDe_sizeRob;
 	/*******************Cables de Sistema*************/
	wire[20:0] wire_FeSys;
	wire wire_SysFe, wire_SysWB, wire_MemReset, wire_HDReset, wire_CoreReset, wire_ArReset;
	wire[148:0] wire_SysAll;
	wire[84:0] wire_WBSys;
	wire[65:0] wire_MemSys;
	wire[84:0] wire_HDSys;
	wire wire_SysHD, wire_HDWB, wire_WBHD, wire_SysCa;
	wire[84:0] wire_CaSys;
	/*****************Final Cables de Sisteam************/
	wire[31:0] AlCa_resultFloatIn, AlCa_resultFloatOut, AlWb_dataIn, AlWb_dataOut;
	wire [15:0]	AlCa_resultIntIn, AlCa_resultIntOut, AlCa_addrOutIn, AlCa_addrOutOut, AlCa_pcIn, AlCa_pcOut, AlCa_veIn, AlCa_veOut, AlWb_exceptionIn, AlWb_exceptionOut, AlFe_pcorigen, AlFe_pctarget;
	wire[2:0] AlCa_tamanyIn, AlCa_tamanyOut;																			 												 
	wire AlCa_enableIn, AlCa_enableOut, AlWb_validIn, AlWb_validOut, AlFe_ErrorSalt, AlFe_Salta, AlDe_nopariscabron, AlCa_esLoadIn, AlCa_esLoadOut, AlCa_regDIn, AlCa_regDOut;										 
	/*****************Cables de Lookup i Cache************/
	wire [31:0] LoCa_dataOut, CaWb_dataOut, CaWb_data, LoCa_data;
	wire [15:0] LoCa_PhysicalAddress, LoCa_address, LoCa_addressOut, LoCa_exception, LoCa_exceptionOut, LoCa_PhysicalAddressOut, CaWb_adressOut, CaWb_exceptionOut, CaWb_adress, CaWb_exception;
	wire [1:0] LoCa_sizeOut, LoCa_size;
	wire LoCa_dirtyOut, LoCa_tlbhitOut, LoCa_loadOut, CaWb_validOut, CaWb_valid, LoCa_dirty, LoCa_tlbhit, LoCa_load, LoCa_stopOut;

									  
Fetch modulFetch (.clock(clk),
	.reset(wire_CoreReset),
	.stop(wire_stop),
	.WbFe_itlbwr(wire_DeFe_itlbwr),
	.WbFe_itlbwridx(wire_DeFe_itlbwridx),
	.WbFe_itlbwren(wire_DeFe_itlbwren),	
	.DeFe_pcexception(wire_DeFeOut[15:0]),
	.DeFe_jumpsys(wire_jumpsys),
	.AlFe_pcoriginal(AlFe_pcorigen),
	.AlFe_pctarget(AlFe_pctarget),
	.AlFe_error(AlFe_ErrorSalt),
	.AlFe_salta(AlFe_Salta),
	.SysFe_cacheline(wire_SysAll[63:0]),
	.SysFe_cachewren(wire_SysAll[64]),
	.SysFe_buswe(wire_SysFe),
	.FeDe_pcactual(wire_FeDeIn[15:0]),
	.FeDe_pcmes(wire_FeDeIn[31:16]),
	.FeDe_pcprediction(wire_FeDeIn[47:32]),
	.FeDe_taken(wire_FeDeIn[48]),
	.FeDe_instruction(wire_FeDeIn[64:49]),
	.FeDe_nop(wire_FeDeIn[65]),
	.FeDe_excp(wire_FeDeIn[81:66]),
	.FeSys_address(wire_FeSys[17:2]),
	.FeSys_request(wire_FeSys[0]),
	.FeSys_busAck(wire_FeSys[1]),
	.FeSys_operation(wire_FeSys[20:18]),
	.FeFe_pcout(wire_FeFe_pcout),
	.FeFe_pcin(wire_FeFe_pcin),
	.WbFe_exception(WbFe_interruption)
);	 

ffda #(.n(16))
ff_FeFe (.D(wire_FeFe_pcout),
	.clk(clk),
	.reset(reset),
	.we(wire_DeFe_enable && ~wire_stop),
	.Q(wire_FeFe_pcin)
);		

ffda #(
	.n(82))
ff_FeDe (.D(wire_FeDeIn),
	.clk(clk),
	.reset(reset),
	.we(~wire_stop),
	.Q(wire_FeDeOut)
);

ffda #(	.n(16))
ff_DeFe (.D(wire_DeFeIn),
	.clk(clk),
	.reset(reset),
	.we(~wire_stop),
	.Q(wire_DeFeOut)
);						   

decode modulDecode (.clk(clk),
	.reset(wire_CoreReset),
	.stop(wire_stop),	
	.FeDe_instruccio(wire_FeDeOut[64:49]),
	.FeDe_pcActual(wire_FeDeOut[15:0]),
	.FeDe_pcPrediction(wire_FeDeOut[47:32]),
	.FeDe_pcMes(wire_FeDeOut[31:16]),
	.FeDe_taken(wire_FeDeOut[48]),
	.FeDe_excp(wire_FeDeOut[81:66]),
	.FeDe_NOP(wire_FeDeOut[65]),
	.DeFe_enable(wire_DeFe_enable),
	.DeFe_itlbwr(wire_DeFe_itlbwr), 
	.DeFe_itlbwridx(wire_DeFe_itlbwridx), 
	.DeFe_itlbwren(wire_DeFe_itlbwren),
	.DeFe_pcexception(wire_DeFeIn[15:0]),
	.DeFe_jumpsys(wire_jumpsys),
	.DeAl_eALU(wire_DeAlIn[0]),
	.DeAl_eMUL(wire_DeAlIn[1]),
	.DeAl_eDIV(wire_DeAlIn[2]),
	.DeAl_eFLT(wire_DeAlIn[3]),
	.DeAl_eMEM(wire_DeAlIn[4]),
	.DeAl_eJMP(wire_DeAlIn[5]),
	.DeAl_eIO(wire_DeAlIn[6]),
	.DeAl_eWRB(wire_DeAlIn[7]),
	.DeAl_eMOV(wire_DeAlIn[8]),
	.DeAl_FRB(wire_DeAlIn[9]),
	.DeAl_wMEM(wire_DeAlIn[10]),
	.DeAl_wIO(wire_DeAlIn[11]),
	.DeAl_JMPType(wire_DeAlIn[12]),
	.DeAl_CMP(wire_DeAlIn[13]),
	.DeAl_wTLB(wire_DeAlIn[14]),
	.DeAl_SRB(wire_DeAlIn[15]),
	.DeAl_eFLUSH(wire_DeAlIn[16]),
	.DeAl_eIID(wire_DeAlIn[17]),
	.DeAl_OP(wire_DeAlIn[20:18]),
	.DeAl_intA(wire_DeAlIn[36:21]),
	.DeAl_intB(wire_DeAlIn[52:37]),
	.DeAl_intC(wire_DeAlIn[68:53]),
	.DeAl_floatA(wire_DeAlIn[90:69]),
	.DeAl_floatB(wire_DeAlIn[122:91]),
	.DeAl_memSize(wire_DeAlIn[125:123]),
	.DeAl_pcActual(wire_DeAlIn[141:126]),
	.DeAl_pcPrediction(wire_DeAlIn[157:142]),
	.DeAl_pcMes(wire_DeAlIn[173:158]),
	.DeAl_taken(wire_DeAlIn[189:174]),
	.DeAl_excp(wire_DeAlIn[205:190]),
	.DeAl_eRETI(wire_DeAlIn[207]),
	.DeAl_eHALT(wire_DeAlIn[207]),
	.DeAl_NOP(wire_DeAl_ff_NOP),
	.AlDe_Salt_incorrecte(AlFe_ErrorSalt),
	.DeWb_valid(wire_DeWbIn[0]),
	.DeWb_pc(wire_DeWbIn[16:1]),
	.DeWb_robTail(wire_DeWbIn[19:17]),
	.DeWb_reg(wire_DeWbIn[35:20]),
	.DeWb_destiny(wire_DeWbIn[39:36]),
	.DeWb_latency(wire_DeWbIn[43:40]),
	.DeWb_exception(wire_DeWbIn[59:44]),
	.DeWb_regBypassA(wire_DeWb_regBypassA),
	.DeWb_regTypeA(wire_DeWb_TypeA),
	.DeWb_regBypassB(wire_DeWb_regBypassB),
	.DeWb_regTypeB(wire_DeWb_TypeB),
	.WbDe_pc(WbDe_pc),
	.WbDe_validBypassA(WbDe_validBypassA),
	.WbDe_valueBypassA(WbDe_valueBypassA),
	.WbDe_validBypassB(WbDe_validBypassB),
	.WbDe_valueBypassB(WbDe_valueBypassB),
	.WbDe_issue(WbDe_issue),
	.WbDe_sizeRob(WbDe_sizeRob),
	.WbDe_STROB(WbDe_STROB),
	.WbDe_inout(WbDe_inout),
	.WbDe_exceptionWrite(WbDe_exceptionWrite),
	.WbBus_valid(WbBus_valid),
	.WbBus_destinyWrite(WbBus_destinyWrite),
	.WbBus_dataWrite(WbBus_dataWrite),
	.WbBus_addressWrite(WbBus_adressWrite), 
	.EupDe_interrupcio(1'b0)
);				


ffda #(	.n(208))
ff_DeAl (.D(wire_DeAlIn),
	.clk(clk),
	.reset(wire_DeAl_ff_NOP),
	.we(~wire_stop),
	.Q(wire_DeAlOut)
);					  

ffda #(	.n(60))
ff_DeWb (.D(wire_DeWbIn),
	.clk(clk),
	.reset(reset),
	.we(~wire_stop),
	.Q(wire_DeWbOut)
);
	
	//Falta:
	//Si no ca biestabes treure els in i out		   
alu alumolona (	  					
	.DeAl_eALU(wire_DeAlOut[0]),
	.DeAl_eMUL(wire_DeAlOut[1]),
	.DeAl_eDIV(wire_DeAlOut[2]),
	.DeAl_eFLT(wire_DeAlOut[3]),
	.DeAl_eMEM(wire_DeAlOut[4]),
	.DeAl_eJMP(wire_DeAlOut[5]),
	.DeAl_eIO(wire_DeAlOut[6]),
	.DeAl_eWRB(wire_DeAlOut[7]),
	.DeAl_eMOV(wire_DeAlOut[8]),
	.DeAl_FRB(wire_DeAlOut[9]),
	.DeAl_wMEM(wire_DeAlOut[10]),
	.DeAl_wIO(wire_DeAlOut[11]),
	.DeAl_JMPType(wire_DeAlOut[12]),
	.DeAl_CMP(wire_DeAlOut[13]),
	.DeAl_wTLB(wire_DeAlOut[14]),  //WTF
	.DeAl_SRB(wire_DeAlOut[15]),   //WTF	
	.DeAl_eFLUSH(wire_DeAlOut[16]),//WTF
	.DeAl_eIID(wire_DeAlOut[17]),  //WTF	
	.DeAl_opcode(wire_DeAlIn[20:18]),										
	.DeAl_intA(wire_DeAlOut[36:21]),
	.DeAl_intB(wire_DeAlOut[52:37]),
	.DeAl_intC(wire_DeAlOut[68:53]),
	.DeAl_floatA(wire_DeAlOut[90:69]),
	.DeAl_floatB(wire_DeAlOut[122:91]),
	.DeAl_memsize(wire_DeAlOut[125:123]), 
	.DeAl_pcALU(wire_DeAlOut[141:126]),	
	.DeAl_pcnext(wire_DeAlOut[157:142]), 
	.DeAl_pcmas(wire_DeAlOut[173:158]),
	.DeAl_ve(wire_DeAlOut[205:190]), 

			  	    
	.DeAl_eRETI(wire_DeAlOut[207]),
	.DeAl_eHALT(wire_DeAlOut[207]),	   
	.DeAl_taken(wire_DeAlIn[189:174]),	
	.clk(clk),
	.reset(wire_CoreReset),
	.stopALU(wire_stop),  //No se qui mel pasa		   
			
	.AlFe_pctarget(AlFe_pctarget),
	.AlFe_pcorigen(AlFe_pcorigen),
	.AlFe_ErrorSalt(AlFe_ErrorSalt),
	.AlFe_Salta(AlFe_Salta),							  
	.AlWb_data(AlWb_dataIn),	
	.AlWb_exception(AlWb_exceptionIn),	
	.AlWb_valid(AlWb_validIn),		 
	.AlCa_resultFloat(AlCa_resultFloatIn),
	.AlCa_resultInt(AlCa_resultIntIn),
	.AlCa_addrOut(AlCa_addrOutIn),
	.AlCa_pc(AlCa_pcIn),			  
	.AlCa_ve(AlCa_veIn),			   
	.AlCa_tamany(AlCa_tamanyIn),
	.AlCa_enable(AlCa_enableIn),
	.AlCa_esLoad(AlCa_esLoadIn)		   
);			 
 						
			//FF Alu-Cache
 			ffd #(.n(32))AlCa_resultFloatFF (.D(AlCa_resultFloatIn),.clk(clk),.reset(reset),.we(~wire_stop),.Q(AlCa_resultFloatOut));	
			ffd #(.n(16))AlCa_resultIntFF (.D(AlCa_resultIntIn),.clk(clk),.reset(reset),.we(~wire_stop),.Q(AlCa_resultIntOut));   
			ffd #(.n(16))AlCa_addrOutFF (.D(AlCa_addrOutIn),.clk(clk),.reset(reset),.we(~wire_stop),.Q(AlCa_addrOutOut));   
			ffd #(.n(16))AlCa_pcFF (.D(AlCa_pcIn),.clk(clk),.reset(reset),.we(~wire_stop),.Q(AlCa_pcOut));   
			ffd #(.n(16))AlCa_veFF (.D(AlCa_veIn),.clk(clk),.reset(reset),.we(~wire_stop),.Q(AlCa_veOut));   
			ffd #(.n(3))AlCa_tamanyFF (.D(AlCa_tamanyIn),.clk(clk),.reset(reset),.we(~wire_stop),.Q(AlCa_tamanyOut));			 
			ffd #(.n(1))AlCa_enableFF (.D(AlCa_enableIn),.clk(clk),.reset(reset),.we(~wire_stop),.Q(AlCa_enableOut));	 					 	
			ffd #(.n(1))AlCa_esLoadFF (.D(AlCa_esLoadIn),.clk(clk),.reset(reset),.we(~wire_stop),.Q(AlCa_esLoadOut)); 
			
			//Flip Flop Alu Wb
			ffd #(.n(32))dadesALUWB (.D(AlWb_dataIn),.clk(clk),.reset(reset),.we(~wire_stop),.Q(AlWb_dataOut));	
			ffd #(.n(16))exceptionALUWB (.D(AlWb_exceptionIn),.clk(clk),.reset(reset),.we(~wire_stop),.Q(AlWb_exceptionOut));
			ffd #(.n(1))validesaALUWB (.D(AlWb_validIn),.clk(clk),.reset(reset),.we(~wire_stop),.Q(AlWb_validOut));
			
			//Flip Flop Decode Wb
			/*ffd #(.n(32))dadesALUWB (.D(Bit validesa decode),.clk(clk),.reset(reset),.we(~wire_stop),.Q(DeWb_validEntryDecodeOut));
			ffd #(.n(32))dadesALUWB (.D(AlCa_resultatFloatIn),.clk(clk),.reset(reset),.we(~wire_stop),.Q(DeWb_newEntryNumOut));
			ffd #(.n(32))dadesALUWB (.D(AlCa_resultatFloatIn),.clk(clk),.reset(reset),.we(~wire_stop),.Q(AlWb_ramALUOut));
			ffd #(.n(32))dadesALUWB (.D(AlCa_resultatFloatIn),.clk(clk),.reset(reset),.we(~wire_stop),.Q(AlWb_ramALUOut));
			ffd #(.n(32))dadesALUWB (.D(AlCa_resultatFloatIn),.clk(clk),.reset(reset),.we(~wire_stop),.Q(AlWb_ramALUOut));
			*/
			//DeWb_pcIn es DeAl_pcActual
	
lookup modulLookUp (.clk(clk),
	.Rst_Lo(reset),
	.AlLo_dataFP(AlCa_resultFloatOut), //he de ficar dos senyals
	.AlLo_dataINT(AlCa_resultIntOut),
	.AlLo_address(AlCa_addrOutOut),
	.AlLo_size(AlCa_tamanyOut),
	.AlLo_enable(AlCa_enableOut),
	.AlLo_load(AlCa_esLoadOut),
	.AlLo_exception(AlCa_veOut), //treure les excepcions d'entrada
	.WbBus_valid(WbBus_valid),
	.WbBus_destinyWrite(WbBus_destinyWrite),
	.WbBus_dataWrite(WbBus_dataWrite),
	.WbBus_adressWrite(WbBus_adressWrite),
	.WbCa_itlbwr(wire_DeFe_itlbwr),
	.WbCa_itlbwridx(wire_DeFe_itlbwridx),
	.WbCa_itlbwren(wire_DeFe_itlbwren),
	.LoCa_data(LoCa_data),
	.LoCa_address(LoCa_address),
	.LoCa_size(LoCa_size),
	.LoCa_exception(LoCa_exception),
	.LoCa_dirty(LoCa_dirty),
	.LoCa_tlbhit(LoCa_tlbhit),
	.LoCa_load(LoCa_load),
	.LoCa_PhysicalAddress(LoCa_PhysicalAddress),
	.stop(wire_stop)
);
			//FF LookUp / Cache
 			ffd #(.n(32))LoCa_dataFF (.D(LoCa_data),.clk(clk),.reset(reset),.we(1),.Q(LoCa_dataOut));	
			ffd #(.n(16))LoCa_addressFF (.D(LoCa_address),.clk(clk),.reset(reset),.we(1),.Q(LoCa_addressOut));      
			ffd #(.n(2))LoCa_sizeFF (.D(LoCa_size),.clk(clk),.reset(reset),.we(1),.Q(LoCa_sizeOut));   
			ffd #(.n(16))LoCa_exceptionFF (.D(LoCa_exception),.clk(clk),.reset(reset),.we(1),.Q(LoCa_exceptionOut));   		 
			ffd #(.n(1))LoCa_dirtyFF (.D(LoCa_dirty),.clk(clk),.reset(reset),.we(1),.Q(LoCa_dirtyOut));
			ffd #(.n(1))LoCa_tlbhitFF (.D(LoCa_tlbhit),.clk(clk),.reset(reset),.we(1),.Q(LoCa_tlbhitOut));   
			ffd #(.n(1))LoCa_loadFF (.D(LoCa_load),.clk(clk),.reset(reset),.we(~wire_stop),.Q(LoCa_loadOut));   
			ffd #(.n(16))LoCa_PhysicalAddressFF (.D(LoCa_PhysicalAddress),.clk(clk),.reset(reset),.we(1),.Q(LoCa_PhysicalAddressOut));			 
			ffd #(.n(1))stopFF (.D(wire_stop),.clk(clk),.reset(reset),.we(1),.Q(LoCa_stopOut));

 cache modulCache (.clk(clk),
 	.LoCa_data(LoCa_dataOut),
	.LoCa_address(LoCa_addressOut),
	.LoCa_size(LoCa_sizeOut),
	.LoCa_exception(LoCa_exceptionOut),
	.LoCa_dirty(LoCa_dirtyOut),
	.LoCa_tlbhit(LoCa_tlbhitOut),
	.LoCa_PhysicalAddress(LoCa_PhysicalAddressOut),
	.LoCa_stop(wire_stop),
	.LoCa_load(LoCa_loadOut),
	.Bus_Data_I(wire_SysAll[63:0]),
	.Bus_ack(wire_SysAll[64]),
	.Bus_grant(wire_SysAll[65]),
	.SysCa_grant(wire_SysCa),
	.CaWb_valid(CaWb_valid),
	.CaWb_data(CaWb_data),
	.CaWb_adress(CaWb_adress),
	.CaWb_exception(CaWb_exception),
	.Ca_Data_O(wire_CaSys[84:21]),
	.CaSys_address(wire_CaSys[20:5]),
	.CaSys_req(wire_CaSys[0]),
	.CaSys_ctl(wire_CaSys[4:2]),
	.stop(wire_stop)
);
			
			//FF Cache / WB
 			ffd #(.n(1))CaWb_validFF (.D(CaWb_valid),.clk(clk),.reset(reset),.we(~wire_stop),.Q(CaWb_validOut));	
			ffd #(.n(32))CaWb_dataFF (.D(CaWb_data),.clk(clk),.reset(reset),.we(~wire_stop),.Q(CaWb_dataOut));   
			ffd #(.n(16))CaWb_adressFF (.D(CaWb_adress),.clk(clk),.reset(reset),.we(~wire_stop),.Q(CaWb_adressOut));   
			ffd #(.n(16))CaWb_exceptionFF (.D(CaWb_exception),.clk(clk),.reset(reset),.we(~wire_stop),.Q(CaWb_exceptionOut));
			
writeback modulWriteBack (.clk(clk),
	.stop(wire_stop),
	.Rst_wb(wire_CoreReset),
	.WbDe_valid(wire_DeWbOut[0]),
	.DeWb_pc(wire_DeWbOut[16:1]),
	.DeWb_robTail(wire_DeWbOut[19:17]),
	.DeWb_reg(wire_DeWbOut[35:20]),
	.DeWb_destiny(wire_DeWbOut[39:36]),
	.DeWb_latency(wire_DeWbOut[43:40]),
	.DeWb_exception(wire_DeWbOut[59:44]),
	.DeWb_regBypassA(wire_DeWb_regBypassA),
	.DeWb_regTypeA(wire_DeWb_TypeA),
	.DeWb_regBypassB(wire_DeWb_regBypassB),
	.DeWb_regTypeB(wire_DeWb_TypeB),
	.AlWb_data(AlWb_dataOut),
	.AlWb_exception(AlWb_exceptionOut),
	.AlWb_valid(AlWb_validOut),
	.CaWb_valid(CaWb_validOut),
	.CaWb_data(CaWb_dataOut),
	.CaWb_adress(CaWb_adressOut),
	.CaWb_exception(CaWb_exceptionOut),
	.Bus_Data_I(wire_SysAll[63:0]),
	.SysWb_Gnt(wire_SysWB),
	.Bus_ACK(wire_SysAll[64]),
	.WbFe_interruption(WbFe_interruption),
	.WbBus_valid(WbBus_valid),
	.WbBus_destinyWrite(WbBus_destinyWrite),
	.WbBus_dataWrite(WbBus_dataWrite),
	.WbBus_adressWrite(WbBus_adressWrite),
	.WbDe_exceptionWrite(WbDe_exceptionWrite),
	.WbDe_pc(WbDe_pc),
	.WbDe_validBypassA(WbDe_validBypassA),
	.WbDe_valueBypassA(WbDe_valueBypassA),
	.WbDe_validBypassB(WbDe_validBypassB),
	.WbDe_valueBypassB(WbDe_valueBypassB),
	.WbDe_issue(WbDe_issue),
	.WbDe_sizeRob(WbDe_sizeRob),
	.WbDe_STROB(WbDe_STROB),
	.WbDe_inout(WbDe_inout),
	.WbSys_Req(wire_WBSys[0]),
	.WbSys_Adr(wire_WBSys[16:1]),
	.WbSys_Data_O(wire_WBSys[84:20]),
	.WbSys_Ctl(wire_WBSys[19:17])
);	

  bus modulBus (.clk(clk),
	.reset(wire_ArReset),
	.FeSys_Req(wire_FeSys[0]),
	.CaSys_Req(wire_CaSys[0]),
	.WBSys_Req(wire_WBSys[0]),
	.HDSys_Req(wire_HDSys[0]),
	.CaSys_ACK(wire_CaSys[1]),
	.FeSys_ACK(wire_FeSys[1]),
	.MemSys_ACK(wire_MemSys[65]),
	.HDSys_ACK(wire_HDSys[84]),
	.WB_Data_O(wire_WBSys[84:20]),
	.HD_Data_O(wire_HDSys[83:20]),
	.Ca_Data_I(wire_CaSys[84:21]),
	.Mem_Data_I(wire_MemSys[64:0]),
	.FeSys_Adr(wire_FeSys[17:2]),
	.CaSys_Adr(wire_CaSys[20:5]),
	.WBSys_Adr(wire_WBSys[16:1]),
	.HDSys_Adr(wire_HDSys[19:4]),
	.FeSys_Ctl(wire_FeSys[20:18]),
	.CaSys_Ctl(wire_CaSys[4:2]),
	.WBSys_Ctl(wire_WBSys[19:17]),
	.HDSys_Ctl(wire_HDSys[3:1]),
	.SysFe_Gnt(wire_SysFe),				 //output
	.SysCa_Gnt(wire_SysCa),				 //output
	.SysHD_Gnt(wire_SysHD),				 //output
	.SysWB_Gnt(wire_SysWB),				 //output
	.Bus_Gnt(wire_SysAll[65]),					  //output
	.Bus_Data_I(wire_SysAll[63:0]),		  //output
	.Bus_Data_O(wire_SysAll[148:85]),			  //output
	.Bus_Adr(wire_SysAll[84:69]),					  //output
	.Bus_Ctl(wire_SysAll[68:66]),					  //output
	.Bus_ACK(wire_SysAll[64])			  //output
);	

memoria modulMem(.clk(clk),
	.reset(wire_MemReset),
	.Bus_Data_O(wire_SysAll[148:85]),
	.Bus_Adr(wire_SysAll[84:69]),
	.Bus_Ctl(wire_SysAll[68:66]),
	.Bus_ACK(wire_SysAll[64]),
	.Bus_Gnt(wire_SysAll[65]),
	.MemSys_ACK(wire_MemSys[65]), //output
	.MemData_I(wire_MemSys[64:0])	 //output
);
hd modulHD (.clk(clk),
	.reset(wire_HDReset),
	.HDSys_ACK(wire_HDSys[84]),	 //output
	.HDSys_Adr(wire_HDSys[19:4]),	 //output
	.HDSys_Ctl(wire_HDSys[3:1]),	  //output
	.HDSys_Req(wire_HDSys[0]),	  //output
	.HD_Data_O(wire_HDSys[83:20]),	  //output
	.SysHD_Gnt(wire_SysHD),
	.Bus_Data_I(wire_SysAll[63:0]),
	.Bus_Data_O(wire_SysAll[148:85]),
	.Bus_Adr(wire_SysAll[84:69]),
	.Bus_Ctl(wire_SysAll[68:66]),
	.Bus_ACK(wire_SysAll[64]),
	.Bus_Gnt(wire_SysAll[65]),
	.HD_Int(wire_HDWB),			  //output
	.HD_Int_ACK(wire_WBHD)			  
);
reset modulReset (.clk(clk),
	.reset(reset),		   //input
	.Mem_Reset(wire_MemReset),	  //output
	.HD_Reset(wire_HDReset),	  //output
	.Ar_Reset(wire_ArReset),	  //output
	.Core_Reset(wire_CoreReset)	  //output
);
endmodule
